Improving Min-cut Placement for VLSI Using Analytical Techniques

Over the past few decades, several powerful placement algorithms have been used successfully in performing VLSI placement. With the increasing complexity of the VLSI chips, there is no clear dominant placement paradigm today. This work attempts to explore hybrid algorithms for large-scale VLSI placement. Our work aims to evaluate existing placement algorithms, estimate the ease of their reuse, and identify their sensitivities and limitations. We study particular aspects of large-scale placement and particular types of netlists on which cause commonly known placement algorithms produce strikingly sub-optimal layouts. Our work points out that significant room for improvement remains in terms of robustness of placement algorithms. Indications are that combining multiple placement algorithms is a worthwhile approach to improve performance on multiple types of netlists. In practice, it is important to have a robust and efficient linearsystem solver for VLSI analytical placement. To this end, we describe the design of a parallel variant for linear systems derived from VLSI analytical placement problems.